|DATE DE PUBLICATION||2015-Jun-01|
|TAILLE DU FICHIER||8,23 MB|
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D ...
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interfac Die Stacking (3D) Microarchitecture - IEEE Conference Publication